Keynote Talk: Insect Flight – From Biology to Technology
Dubi Benyamini (Israel Aerospace Industries Ltd. & The Israeli Lepidopterists Society)
 I will tell the story of the development, production, and test-flying of our robotic butterflies. The first part of the talk will discuss our inspiration: animal flight; I will survey the evolution of natural flight from the first flying insect through flying reptiles, mammals and birds, to nowadays butterflies. The second part of the talk will focus on bio mimicry and on how we’ve built our robotic butterflies, discussing their structure, flight controls, power source, motor, electrical system, communication, and vision. Tomer Hirschfeld (Electrical Engineer) and Guy Marom (Aeronautical Engineer) will participate in the talk and demonstration.

Dubi Benyamini was born in 1941, in Haifa, under Mandatory British Palestine. In high school, he studied at the Haifa Re'ali, and later he obtained a BSc in Mechanical Engineering (1963) and a MSc in Aeronautical Engineering (1965) from the Technion. He served in the Israeli Airforce as an engineer (1963-1969), and, after finishing his military service, he joined the IAI (Israel Aerospace Industries Ltd.), where he was involved in the engineering of tens of aircrafts and unmanned aerial vehicles. Since 2006, Benyamini is the (founding) manager of the Micro Robotics Labs in the Military Aircraft Group of IAI. Since 2007, he is the CEO of 4D MicroRobotics Ltd.


Benyamini is also the President of the Israeli Lepidopterists Society and a world authority of the biology of the blues (Butterfly family Lycaenidae) of Southern South American Andes and Patagonia. He is an amateur Lepidopterist from the age of 9. He discovered over 30 species new to science. He is the author of 2 books and over 200 scientific papers on butterflies. 

Prof. Eran Yahav

Israel Aerospace Industries Ltd. & The Israeli Lepidopterists Society
This talk will present a framework for synthesizing efficient synchronization in concurrent programs, a task known to be difficult and error-prone when done manually. The framework is based on abstract interpretation and can infer synchronization for infinite state programs. Given a program, a specification, and an abstraction, we infer synchronization that avoids all (abstract) interleavings that may violate the specification, but permits as many valid interleavings as possible. The talk will show application of this general idea for automatic inference of atomic sections and memory fences in programs running over relaxed memory models.
(Joint work with Martin Vechev, Michael Kuperstein and Greta Yorsh.)

Flat Datacenter Storage
Dr. Jeremy Elson (Microsoft Research @ Redmond)

Flat Datacenter Storage (FDS) is a high-performance, fault-tolerant, large-scale, locality-oblivious blob store. Using a novel combination of full bisection bandwidth networks, data and metadata striping, and flow control, FDS multiplexes an application's large-scale I/O across the available throughput and latency budget of every disk in a cluster. FDS therefore makes many optimizations around data locality unnecessary. Disks also communicate with each other at their full bandwidth, making recovery from disk failures extremely fast. FDS is designed for datacenter scale, fully distributing metadata operations that might otherwise become a bottleneck.

FDS applications achieve single-process read and write performance of more than 2 GB/s. We measure recovery of 92 GB data lost to disk failure in 6.2s and recovery from a total machine failure with 655 GB of data in 33.7s. Application performance is also high: we describe our FDS-based sort application which set the 2012 world record for disk-to-disk sorting. 

Jeremy Elson is a Senior Researcher at Microsoft. He received his Ph.D. from UCLA in 2003. He has worked in wireless sensor networks, time synchronization, online mapmaking, CAPTCHAs, and distributed storage. He also enjoys riding bicycles, flying airplanes, photography, and building DIY electronics.

 Challenges in Evaluating Parallel Job Schedulers
Prof. Dror Feitelson (The Hebrew University)


In order to evaluate parallel job schedulers one needs to use representative workloads. We'll trace the progress in this area over the past 15-20 years, including the use of workload traces from production systems, the incorporation of feedback effects, and the recent idea of using workload re-sampling. These innovations have led to dramatic changes in how we think about evaluating such systems and what we can do. For example, once we understand that system performance has a feedback effect on the workload, the implication is that there is no such thing as "a representative workload". Rather, we need to understand how users react to system performance, and incorporate this behavior in our simulations. In addition, we'll discuss issues like simulating the system under different load conditions, and the possibilities of modifying recorded traces. 

Dror Feitelson is on the faculty of the School of Computer Science and Engineering at the Hebrew University of Jerusalem, where he heads the experimental systems lab. He also maintains the Parallel Workloads archive, and is the founding co-organizer of the series of workshops on Job Scheduling Strategies for Parallel Processing, now in its 17th year.

Advanced Communication and Interconnect Technologies
Michael Kagan (Mellnox)
We are in the midst of one of the biggest transitions in the technology history, when computing and storage become a service, like electricity at home. Communication technology developed in the 20th century is running out of steam when deployment faces challenges of the 21st century, notably, cloud data centers. This talk will discuss key communication challenges, and it will overview advanced technologies developed at Mellanox to address them. 
Michael Kagan is a co-founder of Mellanox and has served as CTO since January 2009. Previously, Mr. Kagan served as vice president of architecture from May 1999 to December 2008. From August 1983 to April 1999, Mr. Kagan held a number of architecture and design positions at Intel Corporation. While at Intel Corporation, between March 1993 and June 1996, Mr. Kagan managed the Pentium MMX design, and from July 1996 to April 1999, he managed the architecture team of the Basic PC product group. Mr. Kagan holds a Bachelor of Science in Electrical Engineering from the Technion — Israel Institute of Technology.

Microprocessors’ Microarchitecture – Opportunities and Challenges
Prof. Uri Weiser  (Technion)
For decades, computing industry trends have been driven by Moore’s law. Some elements of this trend are changing while power and energy consumption become limiting factors. The shift to multicore is an intermediate solution only. Much greater changes are needed so as to continue the growth of computing capabilities within a specific power envelop. The introduction of new technologies will potentially drive these changes. For example, new advances in Resistive Memory devices (and their silicon proximity to the logic devices) provide an opportunity for new thinking in computer architecture.

This talk will present "Memory Intensive Architecture" (MIA), which is a first step towards creating a taxonomy that assesses the potential impact of Resistive Memory devices on computer architecture. I will give several examples that map to this taxonomy, ranging from usage-specific memory subsystem (denoted "NAHALAL'), through dynamic usage of Memory in multi-engine environment (multicore vs. multithread), to the MIA pipelined multithreading concept. These examples, which are just the tip of the iceberg, share a common insight: that the proximity of new dense memory cells close to processor logic will undoubtedly initiate new computer architectural concepts.

Uri Weiser is a Professor at the Electrical Engineering department, the Technion IIT and is involved with numerous Hi Tech companies. He received the bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City.

Uri worked at Intel from 1988-2006. At Intel, Uri initiated the definition of the Pentium® processor, drove the definition of Intel's MMX™ technology, co-invented the Trace Cache, co-managed the new Intel Microprocessor Design Center at Austin, Texas and initiated an Advanced Media applications research activity. Uri was appointed to be an Intel Fellow in 1996, in 2002 he became an IEEE Fellow, and in 2005 an ACM Fellow.
Prior to his career at Intel, Uri worked for the Israeli Department of Defense as a research and system engineer and later at National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.

Uri was an Associate Editor of IEEEMicro Magazine (1992-2004) and is an Associate Editor of Computer Architecture Letters.

Prof. Eran Tromer

Tel Aviv University

Architectural side channels and their mitigation

Security of modern computer systems relies heavily on the ability to enforce separation between mutually-untrusting processes or virtual machines. The communication between theses processes/VMs is supposedly controlled by the platform (OS, VMM and hardware) according to the system administrator's policy. Alas, information flow is a fickle thing: subtle and unexpected interaction between processes can convey information, and thereby violate enforcement of separation. Such "side channels" have long been the bane of secure system partitioning. In recent years, they have been recognized as especially pertinent in the age of multitenancy in cloud computing. Additionally, highly potent, high-bandwidth side channels have been identified and demonstrated, exploiting low-level architectural effects such as contention among VMs for shared CPU cache resources. This talk will survey the state of the art in the exploitation and mitigation of architectural side channels, and raise important open challenges.

Challenges and Innovations in Creating Energy Efficient Platforms
Dr. Efi Rotem (Intel)

Energy consumption of contemporary data centers has reached a critical mass that impacts the world energy ecosystem. At the other side of the spectrum, client computers are evolving into smaller, thinner and lighter devices, which demand more compute capability but operate on battery in highly constrained physical enclosures. In this talk, I will present specific examples of how Intel has solved some of the problems concerning energy consumption at both ends of the spectrum, and I will highlight trends and future challenges.